Job Description
Fresh Electronics Engineers will be provided on-the-job training for one year & will be part of the team responsible for enhancing the world’s largest portfolio of Verification IPs.
Desired Candidate Profile
Students from good engineering colleges
Minimum 70% in BE, XII & X
Sound Digital Design fundamentals & knowledge of microprocessors is essential
Knowledge of Verilog, C/C++ and OO concepts is preferred
Company Profile
nSys Verification Suite family is the world’s largest portfolio of Verification IPs. Global leaders in Semiconductor, System Houses, Networking & Storage industries use our products to accelerate their ASIC/SoC designs. We have offices in Delhi & CA
Contact Details
Company Name:
nSys Design Systems Pvt. Ltd.
Website:
http:// www.nsysinc.com
Executive Name:
Shilpa
Address:
NSYS Design Systems
B-09, 707 ITL Twin Tower Netaji Subhash Place
Pitampura
NEW DELHI,Delhi,India 110034
Email Address : hr@nsysinc.com (you can send your resume at this address)